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(R)
ESDAxxSC5 ESDAxxSC6
A.S.D.TM
Application Specific Discretes
QUAD TRANSIL ARRAY FOR ESD PROTECTION
APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as : - Computers - Printers - Communication systems - Cellular phone handsets and accessories - Other telephone set - Set top boxes FEATURES
s s
SOT23-5L (SC-59) ESDAxxSC5 FUNCTIONAL DIAGRAM SOT23-5L
SOT23-6L (SC-59) ESDAxxSC6
s
4 Unidirectional TransilTM Functions Low leakage current: IR max. < 20 A at VBR 500 W Peak pulse power (8/20 s)
DESCRIPTION The ESDAxxSC5 and ESDAxxSC6 are monolithic voltage suppressors designed to protect components which are connected to data and transmission lines against ESD. They clamp the voltage just above the logic level supply for positive transients, and to a diode drop below ground for negative transient. BENEFITS High ESD protection level : up to 25 kV High integration Suitable for high density boards
1 2 3
5
4
SOT23-6L
COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 : level 4 15kV (air discharge) 8kV (contact discharge) MIL STD 883E-Method 3015-7 : class3B (human body model)
1 2 3
6 5 4
May 2002 Ed: 6F
1/9
ESDAxxSC5 / ESDAxxSC6
ABSOLUTE MAXIMUM RATINGS (Tamb = 25C) Symbol VPP Test conditions ESD discharge - MIL STD 883E - Method 3015-7 IEC61000-4-2 air discharge IEC61000-4-2 contact discharge Peak pulse power (8/20s) note1 ESDA5V3SCx ESDA6V1SCx ESDA14V2SCx ESDA17SC6 ESDA19SC6 ESDA25SC6 Tj Tstg TL Top Junction temperature Storage temperature range Lead solder temperature (10 second duration) Operating temperature range Value 25 Unit kV
PPP
500 300
W W
150 -55 to +150 260 -40 to +125
C C C C
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VRM VBR VCL IRM IPP Parameter Stand-off voltage Breakdown voltage Clamping voltage Leakage current Peak pulse current Voltage temperature coefficient Capacitance Dynamic resistance Forward voltage drop
Rd
I IF
VBR VCL V RM VF I RM V
T
C Rd VF
I PP
2/9
ESDAxxSC5 / ESDAxxSC6
VBR Types min. @ IR IRM @ VRM max. Rd typ. note 1 V ESDA5V3SC5 ESDA5V3SC6 ESDA6V1SC5 ESDA6V1SC6 ESDA14V2SC5 ESDA14V2SC6 ESDA17SC6 ESDA19SC6 ESDA25SC6 5.3 6.1 14.2 17 19 25 V 5.9 7.2 15.8 19 21 30 mA 1 1 1 1 1 1 A 2 20 5 0.075 0.1 1 V 3 5.25 12 14 15 24 m 230 350 650 700 800 1000 T max. note 2 10-4/C 5 6 10 10 8.5 10 C typ. 0V bias pF 280 190 100 85 80 60 V 1.25 1.25 1.25 1.2 1.2 1.2 mA 200 200 200 10 10 10 VF @ max. IF
max.
note 1 : Square pulse, Ipp = 15A, tp=2.5s. note 2 : VBR = T* (Tamb -25C) * VBR (25C)
CALCULATION OF THE CLAMPING VOLTAGE USE OF THE DYNAMIC RESISTANCE The ESDA family has been designed to clamp fast spikes like ESD. Generally the PCB designers need to calculate easily the clamping voltage VCL. This is why we give the dynamic resistance in addition to the classical parameters. The voltage across the protection cell can be calculated with the following formula:
VCL = VBR + Rd IPP
As the value of the dynamic resistance remains stable for a surge duration lower than 20s, the 2.5s rectangular surge is well adapted. In addition both rise and fall times are optimized to avoid any parasitic phenomenon during the measurement of Rd.
Where Ipp is the peak current through the ESDA cell. DYNAMIC RESISTANCE MEASUREMENT The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the classical 8/20s and 10/1000s surges.
I Ipp
2s tp = 2.5s
t
2.5 s duration measurement wave.
3/9
ESDAxxSC5 / ESDAxxSC6
Fig. 1: Peak power dissipation versus initial junction temperature.
Ppp [Tj initial] / Ppp [Tj initial=25C] 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
5000
Fig. 2: Peak pulse power versus exponential pulse duration (Tj initial = 25 C).
Ppp(W)
ESDA5V3SC5/SC6 & ESDA6V1SC5/SC6
1000
ESDA14V2SC5/SC6 ESDA17SC6 ESDA19SC6 ESDA25SC6
Tj initial(C) 0 25 50 75 100 125 150
100 1
t s) p( 10 100
Fig. 3: Clamping voltage versus peak pulse current (Tj initial = 25 C). Rectangular waveform (tp = 2.5 s).
Ipp(A) 50.0
ESDA25SC6 ESDA19SC6
Fig. 4: Capacitance versus reverse applied voltage (typical values).
C(pF) 500
F=1MHz Vosc=30mV
10.0
ESDA5V3SC5/SC6
ESDA17SC6
ESDA14V2SC5/SC6 ESDA6V1SC5/SC6
100
ESDA6V1SC5/SC6
1.0
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6 ESDA17SC6 ESDA19SC6
Vcl(V) 0.1
tp=2.5s
VR(V) 10 1 2 5 10 20
ESDA25SC6
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
50
Fig. 5: Relative variation of leakage current versus junction temperature (typical values).
Fig. 6: Peak forward voltage drop versus peak forward current (typical values).
IR[Tj] / IR[Tj=25C] 500
ESDA17SC6 & ESDA19SC6
IFM(A) 5.00
ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6
ESDA5V3SC5/SC6
ESDA14V2SC5/SC6 & ESDA6V1SC5/SC6
ESDA19SC6 ESDA17SC6
100
1.00
ESDA25SC6
ESDA25SC6
10 Tj(C) 1 25 50 75
ESDA5V3SC5/SC6
0.10
VFM(V)
100 125
0.01 0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4/9
ESDAxxSC5 / ESDAxxSC6
ESD protection by ESDAXXXSCX Electrostatic discharge (ESD) is a major cause of failure in electronic systems. Transient Voltage Suppressors (TVS) are an ideal choice for ESD protection. They are capable of clamping the incoming transient overvoltage to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line and ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground.
I/ O LINES
ESD sensitive device
GND
ESDAxxxSC6 (1connection to GND for ESDAxxSC5)
The ESDAxxSCx array is the ideal board level protection of ESD sensitive semiconductor components. The tiny SOT23-5L and SOT23-6L packages allow design flexibility in the high density boards where the space saving is at a premium. This enables to shorten the routing and contributes to hardening against ESD. ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : The ESDAxxSC5/6 should be placed as close as possible to the input terminals or connectors.
s
s
s
s
s
The path length between the ESD suppressor and the protected line should be minimized All conductive loops, including power and ground loops should be minimized The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible.
5/9
ESDAxxSC5 / ESDAxxSC6
ADVICE FOR OPTIMIZING CIRCUIT BOARD LAYOUT Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended: The ESDA19SC6 should be placed as close as possible to the input terminals or connectors. The path length between the ESD suppressor and the protected line should be minimized. All conductive loops, including power and ground loops should be minimized. The ESD transient return path to ground should be kept as short as possible. Ground planes should be used whenever possible.
s s s s s
TECHNICAL INFORMATION ESD PROTECTION The ESDA19SC6 is particularly optimized to perform ESD protection. ESD protection is achieved by clamping the unwanted overvoltage. The clamping voltage is given by the following formula :
V CL = V BR + Rd Ipp
As shown in figure A1, the ESD strikes are clamped by the transient voltage suppressor. Fig. A1: ESD clamping behavior (example)
Rg
Rd
Vg
VBR
Voutput
Rload
Device to be protected
ESD Surge
ESDA19SC6
To have a good approximation of the remaining voltages at both VI/O side, we provide the typical dynamical resistance value Rd. By taking into account the following hypothesis : Rg > Rd and Rload > Rd we have:
VOutput = V BR + Rd x
Vg Rg
The results of the calculation done for Vg = 8 kV, Rg = 330 (IEC61000-4-2 standard), Vbr = 19 V (typ.) and Rd = 0.80 (typ.) give: VOuput = 38.4 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be a few tenths of volts during a few nanoseconds at the output side.
6/9
ESDAxxSC5 / ESDAxxSC6
ORDER CODE
ESDA
ESD ARRAY
6V1
SC6
PACKAGE: SC5: SOT23-5L SC6: SOT23-6L
VBR min
ORDERING INFORMATION Odering Type ESDA5V3SC5 ESDA5V3SC6 ESDA6V1SC5 ESDA6V1SC6 ESDA14V2SC5 ESDA14V2SC6 ESDA17SC6 ESDA19SC6 ESDA25SC6
s
Marking EC53 ES53 EC61 ES61 EC15 ES15 ES17 ES19 ES25
Package SOT23-5L SOT23-6L SOT23-5L SOT23-6L SOT23-5L SOT23-6L SOT23-6L SOT23-6L SOT23-6L
Weight 16.7 mg 16.7 mg 16.7 mg 16.7 mg 16.7 mg 16.7 mg 16.7 mg 16.7 mg 16.7 mg
Base qty 3000 3000 3000 3000 3000 3000 3000 3000 3000
Delivery mode Tape & reel Tape & reel Tape & reel Tape & reel Tape & reel Tape & reel Tape & reel Tape & reel Tape & reel
Epoxy meets UL94-V0 standard
7/9
ESDAxxSC5 / ESDAxxSC6
PACKAGE MECHANICAL DATA SOT23-5L
A
DIMENSIONS REF. Millimeters Min. A 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 3.00 0.102 0.60 0.004 10 Typ. Max. Min. 1.45 0.035 0.10 0 Inches Typ. Max. 0.057 0.004 0.0512 0.02 0.008 0.118 0.0689 0.0374 0.118 0.024 10
E
A2
e
D
A1
b
A2 b c D E e
1.30 0.035 0.50 0.0137 0.20 0.004 3.00 0.11
e
1.75 0.059
C
A1
H
H L
L
FOOT PRINT
0.95 0.037 0.60 0.024
3.50 0.138
2.30 0.090
mm inch
8/9
1.10 0.043
1.20 0.047
ESDAxxSC5 / ESDAxxSC6
PACKAGE MECHANICAL DATA SOT23-6L DIMENSIONS
A
REF. A
Millimeters Min. 0.90 0 0.90 0.35 0.09 2.80 1.50 0.95 2.60 0.10 3.00 0.102 0.60 0.004 10 Typ. Max. Min. 1.45 0.035 0.10 0
Inches Typ. Max. 0.057 0.004 0.0512 0.02 0.008 0.118 0.0689 0.0374 0.118 0.024 10
E
A2
e
D
A1
b
A2 b c D E e
1.30 0.035 0.50 0.0137 0.20 0.004 3.00 0.11
e
1.75 0.059
C
A1
H
H L
L
FOOT PRINT
0.60 0.024
3.50 0.138
2.30 0.090
mm inch
0.95 0.037
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 9/9
1.10 0.043
1.20 0.047

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